FPGA Doesn’t Repeal Physics

The claim keeps appearing: once mixers and filters become FPGA code, classic receiver measurements become obsolete and sample rate, SFDR or ENOB take over. No. Those numbers describe different stimuli and different limits. An honest SDR comparison starts by naming the signal environment, reference plane, bandwidth, gain state and decision threshold.

Digital Architecture Moves the Boundary

A direct-sampling receiver can eliminate analog mixers and IF stages, then create several sharply filtered channels in an FPGA. A hybrid SDR can digitize an analog IF. Both can offer excellent filter repeatability, multiple simultaneous receivers, spectrum displays, digital calibration, flexible AGC and feature changes without rebuilding the RF hardware.

Those are real advantages. The signal still reaches analog protection, filters, switches, attenuators, amplifiers, an ADC driver, the converter input and a sampling clock before the FPGA can act. Any of those stages can compress, generate intermodulation, add noise or create a spur. Digital arithmetic also has finite word length and saturation, although a well-scaled pipeline can make its contribution negligible compared with the analog and converter limits.

The practical boundary is simple: DSP can reject energy that remains separable in frequency, time, code or space. Ordinary linear filtering cannot identify an in-band distortion product as false merely because it was generated by the receiver. Once the ADC clips, information about the incident waveform has also been lost. Special cancellation or reconstruction methods need extra knowledge and margin; they are not a replacement for front-end headroom.

One Number Cannot Describe Every Strong-Signal Failure

The active IEEE 1241-2023 ADC standard exists precisely because converter metrics require common terminology and test methods. If two specifications omit different bandwidths, tone levels or gain states, their similar-looking dB values need not be comparable.

DR3 Still Tests a Real Receiver Mechanism

With equal input tones at f₁ and f₂, a third-order nonlinearity creates products at 2f₁ − f₂ and 2f₂ − f₁. Those products can fall close to the test tones and inside a wanted channel. Applying the test at the antenna port exercises the active receiver chain under the declared settings, whether the architecture is superheterodyne, direct conversion or direct sampling.

The ARRL Lab Test Procedures Manual specifies equal tones, defined spacings, the two IMD3 frequencies, MDS and receiver settings. That detail matters. Reducing the measurement bandwidth lowers the measured MDS and can enlarge the reported dynamic range even though the receiver’s large-signal hardware has not changed.

DR3 also needs an end condition. In an ideal cubic region, an intercept-point extrapolation is useful. A real SDR may reach ADC clipping, blocking, AGC action or another spur before an IMD3 product crosses the noise floor. In that case, report the limiting event or a bounded result; do not extend a straight-line intercept model through clipping.

Downstream linear filtering can suppress the applied test tones when they lie outside the selected channel. It cannot generally remove an IMD product already generated at the wanted frequency. This is why two-tone testing remains relevant after the mixer count falls to zero.

RMDR Is a Phase-Noise Test, Not Another Name for DR3

Reciprocal mixing occurs when phase-noise sidebands associated with an oscillator or sampling process convert energy from a strong offset signal into the wanted channel. ETSI’s receiver-parameter guidance explicitly notes the analogous effect of ADC-clock jitter in direct digital down-conversion receivers.

The ARRL method uses the blocker level that raises receiver noise by 3 dB at specified offsets. It also recognizes that a direct-conversion ADC can clip before measurable reciprocal mixing appears; the result then becomes a “better than” bound set by the clipping threshold, not proof of infinite RMDR.

The test generator must be cleaner than the device under test at the offset of interest. Otherwise the generator’s phase noise becomes the result. Analog Devices’ sample-clock spectrum guidance shows how clock and input phase noise couple into an ADC spectrum. FFT horsepower after the converter cannot undo noise already translated into the channel.

SFDR Needs a Prefix and a Reference

“SFDR” is dangerously compact. For an ADC single-tone FFT, it usually means the RMS signal divided by the largest discrete spur and may be stated in dBc or dBFS. A two-tone converter test can use the same label with a different stimulus. A whole-receiver spurious-free range may instead refer to the input span between a sensitivity threshold and the level that creates a detectable spur.

Analog Devices’ SINAD, ENOB and SFDR tutorial distinguishes dBc from dBFS and ties SFDR to the largest observed spur. The input frequency, amplitude, sample rate and analyzed spectrum decide which harmonic, interleaving image, clock feedthrough or unrelated spur wins.

SFDR is therefore valuable for spectral cleanliness and false-signal visibility. It does not integrate the continuous noise floor and does not replace a declared two-tone or blocking test. A receiver can have an excellent single-tone SFDR and still be limited by close-spaced IMD3, reciprocal mixing or composite overload.

NPR Exercises Composite Loading

Noise power ratio applies band-limited Gaussian noise with a narrow, deep notch. After the signal passes through the converter or receiver, noise, clipping and intermodulation refill the notch. NPR is the ratio between the out-of-notch noise density and the residual density in the notch under the declared test method.

Analog Devices’ high-speed ADC test guidance varies composite input level and shows NPR peaking just below clipping, then falling rapidly once clipping begins. That makes NPR useful for a crowded, noise-like load where many components share converter headroom.

It remains a synthetic stimulus. Real carriers may have different amplitudes, crest factor, occupancy and correlation. State the Gaussian-noise bandwidth, notch, RMS loading, backoff and gain state. NPR complements two-tone, blocker and phase-noise tests; it does not overrule them.

SINAD and ENOB Describe a Converter Test Boundary

For an ADC sinewave test, SINAD is the RMS fundamental divided by the root-sum-square of all other measured noise and distortion components, normally excluding DC. The integration bandwidth and treatment of harmonics matter. With the conventional ideal full-scale-sine normalization:

The formula needs an amplitude adjustment when the test sine is below full scale. ENOB is not the number of physically implemented bits, nor a promise that all small codes are monotonic, nor the receiver’s usable dynamic range. It compresses noise and distortion from one defined converter test into an equivalent ideal-bit number.

Do not confuse ADC SINAD with an audio-output SINAD sensitivity test on a demodulating receiver. The latter includes modulation, channel filter, demodulator and audio measurement conditions. Same acronym, different test boundary.

Sample Rate Buys Noise-Bandwidth Leverage, Not Full-Scale Margin

When quantization noise is sufficiently uncorrelated and spread across the Nyquist band, oversampling followed by a digital filter reduces the noise admitted to a narrower channel. The ideal process gain is:

Analog Devices’ quantization-noise tutorial derives this bandwidth relationship and also warns that quantization error is not always white and uncorrelated. Under the ideal assumption, doubling sample rate at fixed bandwidth yields 3 dB, and a fourfold oversampling ratio yields about 6 dB—one bit of noise-equivalent improvement after suitable filtering.

That gain does not raise the converter’s full-scale voltage. It does not prevent an LNA, driver or ADC from compressing. It does not average away deterministic harmonics, interleaving spurs or clock-coupled noise. A narrower FFT bin or channel filter can make the displayed noise floor fall while the largest tolerable blocker remains unchanged.

ADC Headroom Is a Composite-Signal Problem

The ADC sees the instantaneous sum of wanted signals, blockers, noise and any out-of-band energy that survives analog filtering. Full scale is a peak boundary, while band power meters and noise specifications are often RMS quantities. Crest factor therefore matters: a noise-like or multicarrier waveform can clip on peaks even when its average level looks comfortable.

Preselection removes unwanted energy before it consumes ADC range. Attenuation creates headroom but also reduces the wanted signal. Preamplifier gain can improve system noise performance when external noise is low, yet it spends headroom. The useful setting depends on antenna noise, blocker field strength, analog noise figure, converter noise density and the actual gain map.

A receiver comparison must record preamp, attenuator, RF-gain, AGC, preselector, filter bandwidth, sample rate, decimation and firmware state. If the radio changes gain automatically during a test, the state transition is part of the result.

What SDRs Genuinely Improve

• Reconfigurable selectivity: steep, repeatable filters and several independent channels can be created after successful digitization.
• Processing gain: wideband sampling plus narrow digital filtering can improve in-channel noise performance under the stated assumptions.
• Calibration and compensation: predictable gain, phase, DC and quadrature errors can often be characterized and compensated.
• Visibility: panadapters, waterfalls and recording expose activity over a wide span and improve operating efficiency.
• Adaptation: firmware can refine AGC, noise reduction, demodulation, channelization and—in a transmitter with suitable feedback—predistortion.
• Architectural economy: direct sampling can remove analog conversion stages and their individual drift, alignment and spur mechanisms.

None of these benefits makes every SDR superior to every superheterodyne receiver. They explain what the architecture can do after the RF and converter boundaries have been respected.

Build a Limiting-Mechanism Map

For a defensible comparison, use several measurements under matched conditions:

• Measure MDS or noise figure in a bandwidth relevant to the signal and external-noise environment.
• Measure DR3 at close and wider tone spacings, noting per-tone level and any clipping or blocking limit.
• Measure RMDR and blocking at comparable offsets with sufficiently clean generators.
• Use single- and two-tone SFDR with a declared dBc/dBFS reference and spectrum span.
• Use NPR when composite multicarrier loading resembles the intended service.
• Record ADC SINAD/ENOB, sample rate and process bandwidth as converter evidence—not as a whole-radio verdict.
• Repeat relevant tests across gain, attenuation, preselection and band settings.

The receiver’s useful limit is whichever mechanism fails first in the intended environment. That conclusion is less marketable than one giant number and far more useful.

Engineering References

• IEEE 1241-2023: Terminology and Test Methods for Analog-to-Digital Converters
• ARRL Lab Test Procedures Manual: Noise Floor, Blocking, Reciprocal Mixing and Two-Tone Dynamic Range
• ETSI TR 103 877 V1.1.1: Receiver Dynamic Range and Reciprocal-Mixing Boundaries
• Analog Devices AN-835: High-Speed ADC Testing, Including SFDR, IMD and NPR
• Analog Devices MT-003: SINAD, ENOB, SNR, THD and SFDR
• Analog Devices MT-001: Quantization Noise, Oversampling and Processing Gain
• Analog Devices AN-1386: Sample-Clock and Input Phase Noise in ADC Spectra

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